CL HIL Watchdog Clear

Owning Palette: HIL/CD&Sim/Watchdog

Requirements: Quanser Rapid Control Prototyping Toolkit, LabVIEW 2020 or newer, Control Design and Simulation Module

Description

Clears the watchdog state of a HIL board.

Required Inputs All required inputs must be wired. They always appear as terminals on the VI palette. They also appear in bold text in the context help window for the VI.

board in is a reference to a HIL Board instance that represents the open HIL board. This input must be wired to a valid HIL Board signal, as generated by a HIL Initialize VI.

Outputs

board out is a copy of the HIL Board instance passed to the board in input.

Details

When a board is in the watchdog state it is not possible to write to the outputs. Clearing the watchdog state allows the outputs to be written once again. The watchdog state prevents a VI from overwriting the outputs and negating the safety benefit of watchdog timer expiring. The CL Watchdog Clear VI allows a diagram to recover from watchdog expiry and resume operation.

Feedthrough Behaviour

All input/output pairs of this function have direct feedthrough behaviour.

Examples

RCP CL HIL Watchdog Example

Targets

Target	Supported	Comments
RCP Windows (64-bit) Target	Yes	Fully supported.

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