CL HIL Write Analog (Scalar)

Parent Polymorphic VI: CL HIL Write

Requirements: Quanser Rapid Control Prototyping Toolkit, LabVIEW 2020 or newer, Control Design and Simulation Module

Description

Writes to an analog output channel of a HIL board.

Required Inputs All required inputs must be wired. They always appear as terminals on the VI palette. They also appear in bold text in the context help window for the VI.

board in is a reference to a HIL Board instance that represents the open HIL board. This input must be wired to a valid HIL Board signal, as generated by a HIL Initialize VI.

Recommended Inputs or Dialog Box Options Recommended inputs need not to be wired. They may be selected to appear as terminals or dialog parameters, but show up as terminals by default. They appear in simple text in the context help window for the VI.

analog channel is a channel number indicating the analog input channel to be written. The voltage (or current) written will appear at the analog voltage output.

analog voltage is the analog voltage (or current) written to the specified analog channel.

Outputs

board out is a copy of the HIL Board instance passed to the board in input.

Details

This VI only writes one analog input. When writing from mixed signal types, it is more efficient to use the CL HIL Write Mixed than to include multiple VIs specific to each type of channel.

Feedthrough Behaviour

All input/output pairs of this function have direct feedthrough behaviour.

Examples

	RCP CL HIL Analog Loopback Example	This example is a simple analog loopback test, but it demonstrates a number of important features of RCP.
	RCP CL HIL Position Control Example	This example demonstrates how to use a PID controller to control Quanser's SRV02 experiment.

Targets

Target	Supported	Comments
RCP Windows (64-bit) Target	Yes	Fully supported.

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	CL HIL Read	Reads from analog, digital, encoder and/or other channels of a HIL board.
	CL HIL Read Timebase	Reads from analog, digital, encoder and/or other channels of a HIL board while establishing the timing of the simulation loop via a hardware timebase.